Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - DDS Verilog

Search list

[VHDL-FPGA-Verilog] DDS_Timing

Description: 数字频率合成器DDS，具有和单片机接口的直接数字频率合成器的FPGA实现代码（Verilog）-Digital Frequency Synthesizer
Platform: | Size: 95232 | Author: 胡文静 | Hits:

[VHDL-FPGA-Verilog] DDSVerilog

Description: Verilog 实现的DDS源码，可以配合NiosII软核使用 -Verilog realization of DDS source, you can use with soft-core NiosII
Platform: | Size: 3072 | Author: 张松松 | Hits:

[VHDL-FPGA-Verilog] dds_rom

Description: 此为Verilog编写DDS时，常用模块，为rom模块。-This is the Verilog write DDS, the common module, the module for the rom.
Platform: | Size: 5120 | Author: name | Hits:

[VHDL-FPGA-Verilog] FPGAdds

Description: 用verilog写的DDS程序，请用QuartusII 8.1以上版本打开-DDS program written using verilog, please QuartusII 8.1 or later to open
Platform: | Size: 1613824 | Author: 吴恒 | Hits:

[VHDL-FPGA-Verilog] DDS_Verilogcode

Description: 这是一个数字频率综合器（DDS）的Verilog实现源码，采用Quatoues软件综合和仿真-That this is a digital frequency synthesizer (DDS) of the Verilog implementation source code, synthesis and simulation software with Quatoues
Platform: | Size: 699392 | Author: 追月 | Hits:

[VHDL-FPGA-Verilog] DDS_Adder

Description: DDS加法程序，用verilog程序写成，在FPGA的中实现-DDS addition procedures, written with verilog program, implemented in the FPGA' s
Platform: | Size: 5120 | Author: 胡浩 | Hits:

[VHDL-FPGA-Verilog] design_dds_based_on_verilog

Description: 基于verilog hdl 的DDS设计-The DDS-based design of verilog hdl
Platform: | Size: 397312 | Author: yangyang | Hits:

[VHDL-FPGA-Verilog] fpga_dds_coylone_2

Description: dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog to write, can generate a variety of waveforms, the frequency range available on the M, the performance good.
Platform: | Size: 1718272 | Author: wangmingwei | Hits:

[VHDL-FPGA-Verilog] d_e_g_dds

Description: 基于Verilog HDL的迟早门码元同步方案中的DDS程序，已经仿真通过，可以在FPGA开发板上实现。迟-早门方式实现码元同步在无线通信中有着广泛应用。来自华中科大。-Early-later gate of Verilog HDL-based symbol synchronization scheme in the DDS program, has been through simulation, can be achieved in the FPGA development board. From HUST.
Platform: | Size: 1262592 | Author: ye | Hits:

[VHDL-FPGA-Verilog] DDS_verilog

Description: 采用verilog实现了DDS发生器，源码已通过仿真编译已经板级调试，可直接模块化使用。-Verilog achieved using the DDS generator, source code has been compiled by board-level simulation debugging, modularity can be directly used.
Platform: | Size: 2048 | Author: 杨安娜 | Hits:

[VHDL-FPGA-Verilog] DDS_single

Description: 基于FPGA的单路DDS函数发生器的实现 ，语言为Verilog-FPGA-based single-channel DDS function generator implementation language for Verilog
Platform: | Size: 26933248 | Author: Filter | Hits:

[VHDL-FPGA-Verilog] sixiangzaibosheji

Description: 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70MHz output frequency of the four four-phase sequence of a sinusoidal carrier (phase were 0 °, 90 °, 180 °, 270 °) design. Using Verilog HDL language for the programming and design with the Quartus Ⅱ of the simulation to verify its correctness.
Platform: | Size: 5120 | Author: biyuming | Hits:

[VHDL-FPGA-Verilog] key_sin

Description: PS/2键盘加DDS的verilog 设计-PS/2 keyboard plus the verilog design DDS
Platform: | Size: 1969152 | Author: 刘汉超 | Hits:

[VHDL-FPGA-Verilog] DDS_sine

Description: DDS扫频信号源的FPGA实现，有的是verilog编写，欢迎下载-Sweep frequency signal source of DDS FPGA realizing, have a plenty of verilog write, welcome to download
Platform: | Size: 11176960 | Author: jin | Hits:

[VHDL-FPGA-Verilog] 123_ise9migration

Description: DDS正弦信号发生器verilog的功能强大很实用-dds sin verilog
Platform: | Size: 288768 | Author: 亮晶晶 | Hits:

[VHDL-FPGA-Verilog] dds1

Description: 用ALTERA 公司的fpga芯片，编程语言是VerilogHDL,实现DDS数字信号发生器，可以产生正弦信号，三角信号，矩形信号。-ALTERA company fpga chip, programming languages, Verilog HDL, to achieve the DDS digital signal generator, can generate sine signal, triangle signal, rectangular signal
Platform: | Size: 1576960 | Author: 郭晨 | Hits:

[VHDL-FPGA-Verilog] da--sine

Description: 利用dds方法，通过DA输出正弦波，频率1KHz 频率根据代码可调-DA output sine wave frequency 1KHz (Verilog)
Platform: | Size: 3603456 | Author: 范子剑 | Hits:

[VHDL-FPGA-Verilog] verilog_sine-wave-generator

Description: verilog语言书写的基于DDS相频累加器的正弦波发生器-verilog language of the sine wave generator
Platform: | Size: 13312 | Author: 任健铭 | Hits:

[VHDL-FPGA-Verilog] sin_generate

Description: verilog 实现 dds正弦 函数信号发生器 verilog 实现 dds正弦 函数信号发生器-verilog achieve dds sine function signal generator verilog verilog dds sine function signal generator the dds sine function signal generator
Platform: | Size: 425984 | Author: 陈占田 | Hits:

[VHDL-FPGA-Verilog] verilog_dds

Description: verilog实现dds，用于FPGA产生正弦波，适用于Cyclone 2系列-verilog achieve dds, FPGA is used to generate the sine wave, in the Cyclone Series
Platform: | Size: 16789504 | Author: sunlin | Hits:
« 1 2 ... 5 6 7 8 9 1011 12 13 »

CodeBus www.codebus.net